Chip-makers can design-in failure

Led by engineers Partha Pande (left) and Janardhan Rao Doppa, the team has been exploring chip vulnerabilities as a way to prevent malicious attacks, and decided to have a close look at 3D on-chip networks (NoCs) that link parallel processors in stacked die.


It devised three ‘craftily constructed deleterious attacks’ according to the University, to test the communications system, and found that the additional workload enhanced electromigration-induced stress and cross-talk noise – particularly in through-silicon vias (TSVs).

“We determined how an agent can target the communication system to start malfunctions in the chip,” said Pande. “The role of the communications and the threat had not been clear to the research community before.”

The paper ‘Abetting planned obsolescence by aging 3D networks-on-chip‘, presented at the IEEE/ACM International Symposium on Networks-on-Chip.

“Planned obsolescence may adopt any vulnerability in the NoC to cause the SoC to fail,” according to the paper. “We show how an OEM can craft workloads to generate electromigration-induced stress and crosstalk noise in TSV-based vertical links in the NoC to hasten failure.”

It reveals that deliberately injecting 3-10% more traffic on to a few selected critical vertical links can shorten the lifetime of the on-chip network by 11-25% averaged over the benchmarks used.

The next research step is to develop ways to mitigate the problem, such as automated techniques and algorithms to detect and thwart attacks.

New York University and Duke University collaborated in the project.